This invention relates to common channel signalling insertion/extraction devices using high-speed digital multiplexers.
FIG. 7 shows a conventional common channel signalling insertion/extraction device disclosed in Japanese Laid-Open Patent (Kokai) No. 60-153697. The digital signals 1 for a plurality of dedicated digital signal lines are terminated at digital terminals DTI.sub.1 -DTI.sub.n 2, each consisting of a modulator/demodulator, a frame synchronizer, a frame alignment and detection circuits for various alarm signals for the dedicated digital signal lines. The outputs from the digital terminals DTI.sub.1 -DTI.sub.n 2 are supplied to a multiplexer circuit 3 for multiplexing the digital signals 1. Thus, if there are four digital signal lines at 1.5 Mbps, a signal at more than 6 Mbps multiplexing the four digital signals are output from the multiplexer circuit 3.
The multiplexed signal from the multiplexer circuit 3 is supplied to the receiver side time switch 10a of the receiver/transmitter time switch 10, such that the data portions thereof are separated from the common channel signalling portions. The data and the common channel signals thus separated from each other are input to the digital switching channel 6 and the common channel signalling controller 7, respectively. The outputs of the digital switching channel 6 and the common channel signalling controller 7 are supplied to the transmitter side time switch 10b of receiver/transmitter time switch 10, where the data and the common channel signals are multiplexed. The multiplexed signal from the transmitter side time switch 10b is demultiplexed by the demultiplexer 12 and the resulting separate digital signals are output to the dedicated digital lines via the digital terminals DTI.sub.1 -DTI.sub.n 2.
The receiver side time switch 10a receives the multiplexed signal from the multiplexer circuit 3 and separates one or more common channel signals at 64 Kbps from data portions. Conversely, the transmitter side time switch 10b inserts one or more common channel signals at 64 Kbps at a plurality of predetermined positions of the multiplexed signal. The demultiplexer 12 demultiplexes and branches the signal to the dedicated digital lines via the digital terminals DTI.sub.1 -DTI.sub.n 2.
The common channel signalling controller 7 receives the common channel signalling at 64 Kbps from the receiver side time switch 10a and effects functions such as: the error correction of the data, the establishment of data link with the opposite communicating party, assembly of the data structure, and decoding of the signals within frames. The resulting output of the common channel signalling controller 7 is supplied to the switch controller 8, which is supplied with the data from the digital switching channel 6. The switch controller 8 supplies the data transmitted to the opposite communicating party to the common channel signalling controller 7. In response thereto, the common channel signalling controller 7 assembles the data transmitted to the opposite party, establishes the data link therewith, and outputs the common channel signalling at 64 Kbps to the transmitter side time switch 10b.
The above conventional common channel signalling insertion/extraction device has the following disadvantage. When the capacity of the device is enlarged (for example, when high-speed dedicated digital lines are accommodated or when the multiplexed number of dedicated digital lines are increased), the data transmission rate from the multiplexer circuit 3 to the receiver/transmitter time switch 10 and from the receiver/transmitter time switch 10 to the demultiplexer 12 increases. Thus, the processing speed of the receiver/transmitter time switch 10 should also be increased. Within the receiver side time switch 10a, however, the data and the common channel signals are processed by the same circuit. Thus the reading-out and the writing-out rates of the common channel signals increase accordingly. A common channel signalling controller 7 which can respond to the high-speed input/output becomes necessary.
If such a common channel signalling controller 7 is implemented with the ICs and LSIs that are commercially available, the device becomes expensive, or the number of supported channels must be reduced. Further, since the common channel signals and the data are processed by the same circuit of the receiver/transmitter time switch 10, the failure of the receiver/transmitter time switch 10 directly affects the processing of the common channel signals.